With the increasing development of the semiconductor manufacturing process, the size of the transistor in the integrated circuit is gradually decreased and the operating speed of the integrated circuit is gradually increased. For example, since the operating voltage of the integrated circuit can be reduced to 3.3V or less than 2V, the power consumption can be reduced. However, some kinds of integrated circuits still need high positive voltages or high negative voltages. For example, in a flash memory, a higher positive voltage (e.g. +10V) or a higher negative voltage (e.g. −10V) is used as an erase voltage of the flash memory. Obviously, the positive erase voltage is much higher than the operating voltage, and the negative erase voltage is much lower than the operating voltage. For providing the positive erase voltage or the negative erase voltage, the integrated circuit is usually equipped with a charge pump circuit.
FIG. 1A schematically illustrates a conventional 4-phase charge pump circuit for generating a positive voltage. FIG. 1B is a schematic timing waveform diagram illustrating the clocks for controlling the 4-phase charge pump circuit of FIG. 1A. This 4-phase charge pump circuit is disclosed in U.S. Pat. No. 5,644,534 for example. The 4-phase charge pump circuit is controlled by the clocks F1˜F4. Moreover, the 4-phase charge pump circuit comprises four boosting stages 102, 104, 106, 108 and an output stage To. The four boosting stages 102, 104, 106 and 108 have the same structure. The output terminal of each boosting stage is connected with the input terminal of a next boosting stage. The input terminal of the first boosting stage 102 receives an operating voltage Vcc. The output terminal of the fourth boosting stage 108 is connected with the output stage To. Moreover, an output voltage Vout is outputted from the output stage To.
Moreover, each of the four boosting stages 102, 104, 106 and 108 comprises a single boosting circuit. For example, the boosting circuit of the second boosting stage 104 comprises a precharge transistor Tp, a main transistor Tm, and two capacitors Cp, Cm. Both of the precharge transistor Tp and the main transistor Tm are N-type transistors. The drain terminal of the main transistor Tm is served as the input terminal of the second boosting stage 104. The source terminal of the main transistor Tm is served as the output terminal of the second boosting stage 104. The fourth clock F4 is transmitted to the gate terminal of the main transistor Tm through the capacitor Cp in order to control the on/off statuses of the main transistor Tm. The drain terminal of the precharge transistor Tp is connected with the input terminal of the second boosting stage 104. The source terminal of the precharge transistor Tp is connected with the gate terminal of the main transistor Tm. The gate terminal of the precharge transistor Tp is connected with the output terminal of the second boosting stage 104. Moreover, the first clock F1 is transmitted to the output terminal of the second boosting stage 104 through the capacitor Cm.
As shown in FIG. 1B, the amplitude of each of the clocks F1˜F4 is equal to Vcc (i.e. the operating voltage). Since the high voltage level of the second clock F2 and the fourth clock F4 are not superimposed with each other, the main transistor of the previous boosting stage and the main transistor of the next boosting stage will not be simultaneously turned on. Hereinafter, the operating principles of the conventional 4-phase charge pump circuit will be illustrated by referring to the clocks F1˜F4 of FIG. 1B as well as the second boosting stage 104 and the third boosting stage 106 of FIG. 1A.
Before the time point t1, the fourth clock F4 is at a low-level state. That is, the main transistor Tm of the second boosting stage 104 is turned off. The third clock F3 is at a high-level state. That is, the input terminal of the second boosting stage 104 is pumped to 2Vcc. The first clock F1 is at the low-level state. That is, the output terminal of the second boosting stage 104 is not pumped. Under this circumstance, the voltage at the input terminal of the second boosting stage 104 is higher than the voltage at the output terminal of the second boosting stage 104.
From the time point t1 to the time point t2, the fourth clock F4 is at the high-level state, the third clock F3 is maintained at the high-level state, and the first clock F1 is maintained at the low-level state. That is, the main transistor Tm of the second boosting stage 104 is turned on, and a charging path is created. Under this circumstance, a charging current flows from the input terminal of the second boosting stage 104 to the output terminal of the second boosting stage 104. Consequently, the output terminal of the second boosting stage 104 is charged to 2Vcc theoretically or an elevated level pumped from Vcc as the result of charge sharing between input terminal and output terminal of the second boosting stage 104 practically.
From the time point t2 to the time point t3, the fourth clock F4 is at the low-level state, the third clock F3 is maintained at the high-level state, and the first clock F1 is maintained at the low-level state. That is, the main transistor Tm of the second boosting stage 104 is turned off again. Since the charging path fails to be created, the output terminal of the second boosting stage 104 is maintained at 2Vcc theoretically or the elevated level practically.
At the time point t3, the first clock F1 is switched to the high-level state. That is, the output terminal of the second boosting stage 104 (i.e. the input terminal of the third boosting stage 106) is pumped to 3Vcc or a further boosted level pumped from the previous elevated level. At the time point t4, the third clock F3 is switched to the low-level state. That is, the output terminal of the third boosting stage 106 is not pumped. Under this circumstance, the voltage at the input terminal of the third boosting stage 106 is higher than the voltage at the output terminal of the third boosting stage 106.
From the time point t5 to the time point t6, the second clock F2 is at the high-level state, the first clock F1 is maintained at the high-level state, and the third clock F3 is maintained at the low-level state. That is, the main transistor of the third boosting stage 106 is turned on, and a charging path is created. Under this circumstance, a charging current flows from the input terminal of the third boosting stage 106 to the output terminal of the third boosting stage 106. Consequently, the output terminal of the third boosting stage 106 is charged to 3Vcc theoretically or a second elevated level range pumped from 2Vcc as the result of charge sharing between input terminal and output terminal of the third boosting stage 106 practically.
Since the 4-phase charge pump circuit is controlled by the clocks F1˜F4, the output terminal of the first boosting stage 102 is operated between Vcc and 2Vcc, the output terminal of the second boosting stage 104 is operated between 2Vcc and 3Vcc, the output terminal of the third boosting stage 106 is operated between 3Vcc and 4Vcc, and the output terminal of the fourth boosting stage 108 is operated between 4Vcc and 5Vcc.
Moreover, the transistor of the output stage To is also an N-type transistor. The drain terminal and the gate terminal of the output stage To are both connected with the output terminal of the fourth boosting stage 108. Moreover, an output voltage Vout is outputted from the source terminal of the output stage To. Consequently, during the first clock F1 is at the high-level state, the output stage To is turned on to generate the output voltage Vout of 5Vcc.
From the above discussions, the 4-phase charge pump circuit uses four boosting stages to stagewise pump the operating voltage Vcc four times. Consequently, the positive output voltage Vout from the 4-phase charge pump circuit is equal to 5Vcc (i.e. Vcc+4Vcc=5Vcc). In other words, if the 4-phase charge pump circuit comprises N boosting stages, the output voltage Vout is equal to (N+1)×Vcc.
FIG. 2A schematically illustrates a conventional 4-phase dual-branch charge pump circuit for generating a positive voltage. FIG. 2B is a schematic timing waveform diagram illustrating the clocks for controlling the 4-phase dual-branch charge pump circuit of FIG. 2A. The branch from the upper-half operating voltage Vcc to the output voltage Vout denotes a first branch of the 4-phase dual-branch charge pump circuit, and the branch from the lower-half operating voltage Vcc to the output voltage Vout denotes a second branch of the 4-phase dual-branch charge pump circuit. The circuitry of the first branch and the circuitry of the second branch are identical, except the controlling clocks are in the complementary phase of the 4-phase clocking. Moreover, the 4-phase dual-branch charge pump circuit is controlled by the clocks F1˜F4.
As shown in FIG. 2A, the 4-phase dual-branch charge pump circuit comprises four boosting stages 202, 204, 206, 208 and an output stage 210. The four boosting stages 202, 204, 206 and 208 have the same structure. Each of the four boosting stages 202, 204, 206 and 208 comprises a first boosting circuit and a second boosting circuit, which have the same structure. The first boosting circuit belongs to the first branch, and the second boosting circuit belongs to the second branch.
In the first branch, the output terminal of the first boosting circuit of each boosting stage is connected with the input terminal of the first boosting circuit of a next boosting stage. The input terminal of the first boosting circuit of the first boosting stage 202 receives the operating voltage Vcc. The output terminal of the first boosting circuit of the fourth boosting stage 208 is connected with the output stage 210. In the second branch, the output terminal of the second boosting circuit of each boosting stage is connected with the input terminal of the second boosting circuit of a next boosting stage. The input terminal of the second boosting circuit of the first boosting stage 202 receives the operating voltage Vcc. The output terminal of the second boosting circuit of the fourth boosting stage 208 is connected with the output stage 210.
For example, the first boosting circuit of the first boosting stage 202 comprises a precharge transistor T2, a main transistor T1, and two capacitors C1, C2. Both of the precharge transistor T1 and the main transistor T2 are N-type transistors. The drain terminal of the main transistor T1 is served as the input terminal of the first boosting circuit of the first boosting stage 202. The source terminal of the main transistor T1 is served as the output terminal of the first boosting circuit of the first boosting stage 202. The second clock F2 is transmitted to the gate terminal of the main transistor T1 through the capacitor C1. The drain terminal of the precharge transistor T2 is connected with the input terminal of the first boosting circuit of the first boosting stage 202. The source terminal of the precharge transistor T2 is connected with the gate terminal of the main transistor T1. The gate terminal of the precharge transistor T2 is connected with the output terminal of the first boosting circuit of the first boosting stage 202. Moreover, the third clock F3 is transmitted to the output terminal of the first boosting circuit of the first boosting stage 202 through the capacitor C2.
The output stage 210 comprises two output circuits, which have the same structure. The first output circuit belongs to the first branch, and the second output circuit belongs to the second branch. The first output circuit comprises a capacitor C9, a transistor T9, and a transistor T10. Both of the transistor T9 and the transistor T10 are N-type transistors. The drain terminal of the transistor T9 is connected with the output terminal M of the first boosting circuit of the fourth boosting stage 208. Moreover, an output voltage Vout is outputted from the source terminal of the transistor T9. The second clock F2 is transmitted to the gate terminal of the transistor T9 through the capacitor C9. The drain terminal of the transistor T10 is also connected with the output terminal M of the first boosting circuit of the fourth boosting stage 208. The source terminal of the transistor T10 is connected with the gate terminal of the transistor T9. The gate terminal of the transistor T10 is connected with the output terminal M′ of the second boosting circuit of the fourth boosting stage 208.
The second output circuit comprises a capacitor C9′, a transistor T9′, and a transistor T10′. The drain terminal of the transistor T9′ is connected with the output terminal M′ of the second boosting circuit of the fourth boosting stage 208. The source terminal of the transistor T9′ is connected with the source terminal of the transistor T9 for outputting the output voltage Vout. The fourth clock F4 is transmitted to the gate terminal of the transistor T9′ through the capacitor C9′. The drain terminal of the transistor T10′ is also connected with the output terminal M′ of the second boosting circuit of the fourth boosting stage 208. The source terminal of the transistor T10′ is connected with the gate terminal of the transistor T9′. The gate terminal of the transistor T10′ is connected with the output terminal M of the first boosting circuit of the fourth boosting stage 208.
As shown in FIG. 2B, the amplitude of each of the clocks F1˜F4 is equal to Vcc (i.e. the operating voltage). Since the high voltage level of the second clock F2 and the fourth clock F4 are not superimposed with each other, the main transistor of the previous first boosting circuit and the main transistor of the next first boosting circuit in the first branch will not be simultaneously turned on. The operating principles of the first branch and the second branch of the 4-phase dual-branch charge pump circuit are similar to the operating principles of the 4-phase charge pump circuit of FIG. 1A, and are not redundantly described.
Since the 4-phase dual-branch charge pump circuit is controlled by the clocks F1˜F4, the output terminals of the first boosting circuit and the second boosting circuit of the first boosting stage 202 are operated between Vcc and 2Vcc, the output terminals of the first boosting circuit and the second boosting circuit of the second boosting stage 204 are operated between 2Vcc and 3Vcc, the output terminals of the first boosting circuit and the second boosting circuit of the third boosting stage 206 are operated between 3Vcc and 4Vcc, and the output terminals of the first boosting circuit and the second boosting circuit of the fourth boosting stage 208 are operated between 4Vcc and 5Vcc.
Moreover, during the second clock F2 is at the high-level state, the first output circuit of the output stage 210 may generate the output voltage Vout of 5Vcc. Moreover, during the fourth clock F4 is at the high-level state, the second output circuit of the output stage 210 may generate the output voltage Vout of 5Vcc.
From the above discussions, the 4-phase dual-branch charge pump circuit uses four boosting stages to stagewise pump the operating voltage Vcc four times. If the 4-phase dual-branch charge pump circuit comprises N boosting stages, the output voltage Vout is equal to (N+1)×Vcc. In comparison with the 4-phase charge pump circuit of FIG. 1A, the 4-phase dual-branch charge pump circuit of FIG. 2A has smaller output ripple and potentially higher output efficiency.
Moreover, in case that the N-type transistors of the 4-phase dual-branch charge pump circuit of FIG. 2A are replaced by P-type transistors, another 4-phase dual-branch charge pump circuit for generating a negative voltage is provided. FIG. 3A schematically illustrates a conventional 4-phase dual-branch charge pump circuit for generating a negative voltage. FIG. 3B is a schematic timing waveform diagram illustrating the clocks for controlling the 4-phase dual-branch charge pump circuit of FIG. 3A.
The branch from the upper-half ground voltage to the output voltage Vout denotes a first branch of the 4-phase dual-branch charge pump circuit, and the branch from the lower-half ground voltage to the output voltage Vout denotes a second branch of the 4-phase dual-branch charge pump circuit. The circuitry of the first branch and the circuitry of the second branch are identical. Moreover, the 4-phase dual-branch charge pump circuit is controlled by the clocks F1˜F4.
As shown in FIG. 3A, the 4-phase dual-branch charge pump circuit comprises four boosting stages 302, 304, 306, 308 and an output stage 310. Each of the four boosting stages 302, 304, 306 and 308 comprises a first boosting circuit and a second boosting circuit, which have the same structure. The first boosting circuit belongs to the first branch, and the second boosting circuit belongs to the second branch. Hereinafter, the operations of the 4-phase dual-branch charge pump circuit will be illustrated by referring to a single boosting circuit.
According to the first clock F1 and the third clock F3, when the main transistor of the first boosting circuit is turned on, the voltage at the input terminal of the first boosting circuit is lower than the voltage at the output terminal of the first boosting circuit. Consequently, a charging circuit flows from the output terminal to the input terminal. Under this circumstance, the minimum output voltage is outputted from the output terminal of the first boosting circuit of the last boosting stage 308. As shown in FIG. 3A, since the 4-phase dual-branch charge pump circuit uses four boosting stages to stagewise pump the ground voltage (0V) four times, the output stage 310 may generate the output voltage Vout of −4Vcc.
As known, for designing an integrated circuit, the operating voltage Vcc and the output voltage Vout should be firstly realized, and then the number of boosting stages of the charge pump circuit is determined. That is, after the charge pump circuit is designed, the relationship between the operating voltage Vcc and the output voltage Vout is determined and fails to be changed.
Recently, the fabricating process of the integrated circuit is advanced to the deep sub-micron technology. For example, the operating voltage for the circuit system using the 0.13 μm technology may be 1.8V, 2.5V or 3.3V. After the charge pump circuit is designed, the charge pump circuit fails to be applied to the circuit system with various operating voltages.